1. Field of the Invention
The present invention relates to a semiconductor memory that is internally operable at high speed when tested with a low-speed tester.
2. Description of the Related Art
Recent high-speed microprocessors require high-speed semiconductor memories, in particular, high-speed static random access memories (SRAMs) serving as cache memories. The high-speed SRAMs require high-speed testers to match the speeds of the SRAMs. High-speed testers, however, are expensive, increasing testing costs.
An earlier technique to deal with this problem installed a built-in self test (BIST) circuit in a memory chip to autonomously carry out high-speed testing in the memory chip. FIG. 1 shows a related art that installs a BIST circuit in a memory chip for carrying out high-speed testing. In FIG. 1, a low-speed tester supplies a low-frequency clock signal CK. From the clock signal CK, a clock generator 201 generates a high-frequency internal clock signal CK_int to carry out high-speed testing of the memory. The low-speed tester provides an address A, a command CMD, and input data D. These data pieces are converted into high-speed ones in synchronization with the internal clock signal CK_int by an input data generator 202, a command generator 203, and an address generator 204 installed in the memory chip. The converted data pieces are supplied to an SRAM core 205 to carry out high-speed testing. After the test, the SRAM core 205 provides a high-frequency test result Q_int. The test result Q_int is compared by a comparator 206 with an expected value generated by an expected value generator 207, and the comparator 206 provides a pass or fail comparison result. The comparison result is compressed by a compressor 208, which provides a low-frequency resultant signal.
The BIST circuit of the related art may carry out high-speed testing with a low-speed tester. The related art, however, provides a test result showing only a final pass or fail result. When a fail result is provided, the related art is unable to provide detailed information such as the fail bit map of the tested memory.
The clock generator 201 in the BIST circuit of the related art employs, for example, a phase-locked loop (PLL) 212 shown in FIG. 2. In a normal mode, a buffer circuit 211 of the clock generator 201 amplifies the external clock signal CK, and a multiplexer (MUX) 213 of the clock generator 201 provides the amplified clock signal as the internal clock signal CK_int. In a test mode, the PLL 212 multiplies the frequency of the external clock signal CK by N in synchronization therewith, and the multiplexer 213 selects the frequency-multiplied clock signal as the internal clock signal CK_int. In this way, the clock generator 201 is capable of generating the high-frequency internal clock signal CK_int from a clock signal provided by a low-speed tester.
The PLL 212 in the clock generator 201, however, needs a large circuit area, and therefore, the BIST circuit incorporating the PLL increases the area of the memory chip in which the BIST circuit is installed.
In this way, the BIST circuit of the related art installed in a semiconductor memory to carry out a test at high speed provides a test result showing only a pass or fail result. Namely, the related art is incapable of providing detailed information related to the test result. In addition, the related art employs a PLL to generate a high-speed clock signal to test the memory at high speed. The PLL increases the size of the BIST circuit, complicates the structure of the same, and is unable to precisely control the frequency of the clock signal generated.